Utilization of simulink verification and validation (V&V) and simulink design verifier (SDV) for HVAC controls software

This presentation introduces Simulink Verification and Validation™ and Simulink Design Verifier™ and highlights advanced verification and validation techniques (involving structural coverage analysis and formal methods) for testing various components within the HVAC Controls Software Readiness and Core Engineering groups. The session also summarises some of General Motors’ results and discusses the benefits already obtained and those we hope to achieve in the long run, as well as some of the challenges that confront us

Utilization of simulink verification and validation (V&V) and simulink design verifier (SDV) for HVAC controls software

This presentation introduces Simulink Verification and Validation™ and Simulink Design Verifier™ and highlights advanced verification and validation techniques (involving structural coverage analysis and formal methods) for testing various components within the HVAC Controls Software Readiness and Core Engineering groups. The session also summarises some of General Motors’ results and discusses the benefits already obtained and those we hope to achieve in the long run, as well as some of the challenges that confront us

On the need for a visual notation for ITL

The talk introduces the formal language, Interval Temporal Logic(ITL), discusses the 'lean approach' to formal methods, argues the need for a visual notation for ITL and presents such a visual notation. The talk concludes indicating directions I planned to take for subsequent work towards my PhD

More automated formal methods?! : If so, why, where & how?

Formal Methods (FM) have been around for decades and many have been improving all the time. Automated formal methods techniques and tools have been making a mark in real world applications across industry domains. So, why and where do we need more automation? How much automation is required? This paper attempts to cover an assessment on where I believe we are, based on my own not-so-limited but diverse enough experience in automated industry-strength formal methods and model based systems engineering area, where we might need to get to and possibly how. Key characteristics of future automation needed for success are outlined. No attempt is made to be exhaustive as the world of FMs is vast and the collective work of FM expert researchers, developers and users is needed for exploration – “to boldly meet future challenges which no FM has ever met before”

Interval temporal logic and tempura for the formal specification of real-time and safety-critical systems

This conference presentation covers details on formal specification languages, ITL and its executable subset Tempura, for application to real-time safety-critical systems

Evaluation of formal verification technology at IARC

This is a contributed talk to the International Workshop organised by the Department of Computer Science, University of Warwic

SysML for automotive software development and integration

This conference presentation disseminates, to the wider world, the research work done, within the Premium Automotive R&D programme, on Systems Modelling Language (SysML) that was in its nascent stages of introduction as a standard language for Model Based Systems Engineering. It covers details on work which involved collaboration with Jaguar Land Rover and some supplier(s)

Using simulink and stateflow for model checking of system models

This presentation covers work done at WMG, within the collaborative R&D project PICASSOS, in the area of system-level verification utilising formal methods. It covers the translation of SysML models (including fault modelling and safety mechanisms) to Simulink/Stateflow and its subsequent use for formal verification of Technical Safety Requirements and Safety Goals